To prototype a system it is convenient to have a processor on-chip running at its normal speed, and the logic or other off-chip resources which are ultimately to be integrated onto the chip as an off-chip circuit for prototyping purposes. The off-chip circuit can be for example in the form of an FPGA or emulator and can provide memory resources.
Currently, this involves either bonding-out the processor core so that its signals are available off-chip or using one of the existing off-chip communication ports which are already provided on the chip on which the processor is situated. Such ports are generally serial ports or reduced pin-out ports such as debug ports, and in any event are not provided as dedicated ports for prototyping but have some already existing function.
In a situation where the processor core is bonded-out, there are a number of problems. In the first place, bonding-out of a processor's on-chip interface uses a lot of pins. The processor has to be run at a reduced speed in order for the bond-out interface to function reliably. The limitation on the use of pins means that it is difficult to support platform prototyping where some resources are integrated on-chip and some are not.
Where an existing off-chip communication port is used, there are also difficulties. Many such ports require software assistance to function. This software is not required in the integrated system which is under prototype, which means that the prototype software in the final software will have to be different. In effect, the final software cannot run on the prototype and therefore any testing of the prototype cannot completely match the final product.
Many such ports have an address map footprint which implies that the prototype address map is different from the final integrated address map. This also means that the final software cannot run on the prototype.